The present invention relates to a method of placing marks for alignment accuracy measurement and, more particularly, to a method of placing marks for alignment accuracy measurement in an LSI chip by means of automatic placing and routing CAD (Computer Aided Design) program.
Conventionally, a method has been employed, in which measurement marks for evaluating pattern dimensional accuracy and positioning accuracy are formed, together with a TEG (Test Element Group) for process evaluation, in the peripheral region of the LSI chip in order to measure the dispersion of the dimensional accuracy or displacement of position of the pattern layout of the LSI.
As an example, FIG. 1 schematically shows the pattern layout of an LSI in which a plurality of mega-cells 1, e.g., an arithmetic logic unit and a memory unit, and their peripheral logic circuits (not shown) are placed in an inner chip region 17, and chip peripheral I/O and TEG regions 18, 18a have input and output wiring and process evaluation TEGs 20.
In order to realize high integration of LSIs, the inner circuit comprising the mega-cells 1 and their peripheral logic circuits is usually placed without open spaces as much as possible by using the automatic placing and routing CAD program. Regarding this, the wiring of the I/O region 18, comprising input and output data buses on the peripheral region of the chip, must be routed around in accordance with the package shape and pin configuration, usually resulting in a layout having open spaces.
In order to manufacture an LSI, evaluation of the completeness of interlayer insulation, the contact yield of connections such as contact holes or the like, and evaluation of the partial circuit including transistors must be performed in the manufacturing process. Portions that perform these evaluations are included in the chip peripheral I/O and TEG regions 18, 18a as process evaluation TEGs 20 shown in FIG. 1.
An LSI requires ten-odd times of mask alignment operation in lithography. A high manufacturing yield is assured by evaluating the pattern dimensional accuracy and interlayer positioning accuracy in mask pattern printing process. In order to evaluate the dimensional accuracy and positioning accuracy, a measurement mark block 2 usually comprising a plurality of measurement marks is necessary. The measurement mark block 2 usually changes depending on the mask pattern layers, and different types of marks are used for different LSI functions.
Concerning the dimensional accuracy and positioning accuracy of the LSI pattern layout, in recent years, along with the progress in LSI products in the deep submicron region, dimensional and positioning dispersions of not only the I/O and TEG regions 18, 18a in the chip peripheral region but also the inner circuit placed in the inner chip region 17 have great importance. For this reason, a plurality of measurement marks must be dispersedly placed in the inner chip region 17 in accordance with some method.
As described above, it is not conventionally intended to include exclusive measurement marks for pattern dimensional accuracy and positioning accuracy in the inner chip region 17 of a logic LSI with an irregular pattern layout. Accordingly, the dimensional and positioning dispersions of the LSI pattern placed in the inner chip region 17 are conventionally evaluated by using part of the LSI pattern in place of a measurement mark.
In an actual LSI, its pattern and layout are complicated, and the pattern dependence, proximity effect, and the like are complicatedly related to errors in pattern dimension and position. With the method of using part of the LSI pattern in place of the measurement mark, errors in pattern dimension and position cannot be measured with high precision.
With this conventional method, the layout designer selects part of the LSI pattern as the measurement mark by a manual operation, and the measurement operator measures a pattern selected as the measurement mark, which changes for each time of measurement. Accordingly, it is very difficult to make standardization of measuring operation, leading to measurement errors.
Conventionally, an attempt has also been performed to improve the measurement accuracy of dimension and position of the LSI pattern layout by placing exclusive measurement marks in the logic LSI chip. In this case, when the automatic placing and routing CAD procedure of the logic LSI is ended, the measurement marks are placed by searching open spaces in the chip appropriate for including the measurement marks by a manual operation.
Since this method is performed after the automatic placing and routing CAD procedure, the presence of the open spaces in the chip appropriate for including the measurement marks cannot be guaranteed in advance. If the appropriate open spaces are not present, the automatic placing and routing CAD procedure of the logic LSI must be performed again by the man-machine interactive operation, to forcedly place the open spaces for the measurement marks in the LSI pattern layout.
In this case, since the man-machine interactive operation leaves arbitrariness, standardization of measurement of the dimensional accuracy and positioning accuracy of the LSI pattern layout becomes difficult, causing measurement errors, longer development time, and increasing the cost.